John Cooley, moderator of the E-Mail Synopus Users Group (ESNUG), has been writing detailed trip reports on the annual Design Automation Conference (DAC) for several years now. This conference is the major annual event in the EDA industry year. The influential 2002 report contains no-holds-barred reviews of about 100 EDA tools collated from hundreds of chip designers and for the first time features feedback on Tenison EDA. As the full report comprises roughly 150 print pages, we have highlighted the article covering Tenison EDA below.

223 Engineers Review 2002's Crop of EDA Tools of June 10-14, 2002

by John Cooley

Excerpt from Item 4: Summit, TenisonTech, Virtio, Translogic

"…...Having said all that, I must say that the notion of using C is smart. There's a small company called Tenison EDA that makes a tool called VTOC. VTOC converts Verilog to C. Get it? VTOC.

Anyway, the tool works well, the support is fantastic, and the cost is reasonable. We take our converted Verilog model (note: single source model written in Verilog and we tie it into a full "C" model of our validation board created with a tool developed by a company called Virtio. Again, these guys have a great technology, great support, and very good price. We use this board level model to develop and test the silicon model and its associated board level SW.

At SeaWay Networks, we don't go to tape out until the device is tested with all the production SW that will interact with the device. All of it. We also use this system to introduce real network traffic into the simulation to ensure we are compliant with the "big standard" (i.e. what the world in general is actually doing as opposed to what the spec says.) We pull traffic right off of the network and feed it into the simulation. So, we use C this way and what do we get?

1/ SW/HW co-development virtually eliminating SW/HW API bugs (Thank you very much Tenison EDA and Virtio).

2/ Real world traffic running through a fully simulated system, right down to the flash, virtually eliminating specification interpretation errors.

3/ Developers working with tools that are a fraction of the cost of a single Verilog license. Must be cheap cheap cheap.

4/ A single source device model written in verilog and converted to "C". No maintenance problems there.

5/ Rapid proto validation, the test SW is also written before the first sample device ever arrives. The best part is when our developers are done, the full environment is shipped to our customers as part of our "customer support package". They can write their application SW using the same system. They can run their SW with our SW and our silicon. All of this is done with a high reliability simulation platform proven during our own development cycle. Now that's elegant. Our team has developed five first rev successes ASIC's in a row using tools like this." - Jonathan Adair of Seaway Networks"