It never fails. Just when I think I'm on top of things, someone comes up with an idea that would never have struck me in a thousand years. In this case I'm talking about a product called VTOC from Tenison Technology in England. This little rapscallion translates a Verilog representation of a design into an equivalent cycle-accurate C/C++ model. (Actually, VTOC can also output SystemC if required, but for the rest of this column I'll just reference C/C++ for brevity.)

The resulting C/C++ source code file can subsequently be compiled using whichever ANSI C/C++ compiler you happen to have lying around, and the ensuing compiled binary file can be executed on any processor without license. (Note that at some stage you will have to manually create a C testbench to simulate the compiled model. Alternatively, you can link it into your existing simulation environment by means of the Verilog PLI.)

So why was this a surprise to me? I suppose it was simply that I hadn't thought about it before. I was certainly familiar with the concept of commencing a project by creating a C/C++ model that could be used to prove the design concept, and could also be used for hardware/software co-verification. I was also familiar with the idea of taking such a C/C++ model and translating it into an equivalent Verilog representation suitable for use by traditional EDA tools like synthesis.

What had never struck me was the idea of going the other way -- that is, creating the Verilog model first and then generating its C/C++ equivalent. So why would someone wish to use VTOC? In fact, the hardware description language (HDL) to high-level language (HLL) translation performed by VTOC is really a means to an end, with several possible ends. Of particular interest are the possibilities for simulation speedup and hardware/software co-development.

Every design engineer is interested in speeding up his or her simulations (some of which can run for weeks on a traditional software simulator). The typical simulation speedup options involve investing in a top-of-the-line Verilog simulator (expensive) or using a hardware simulation accelerator/emulator. Tenison claims that the C/C++ models generated by VTOC can run 100 times faster than Verilog-XL and 10 times faster than Verilog-NC from Cadence. This certainly makes VTOC interesting, and they are constantly pushing to make things faster.

The second area of interest is hardware/software co-development, which is gaining in importance, especially since more and more designs include both the processor and logic on the same ASIC/FPGA/SoC. Many industry analysts believe that ES-level (electronic system level) design featuring hardware/software co-development is critical to the success of SoC devices, and high-end EDA suppliers such as Cadence, Mentor, and Synopsys are focusing a great deal of attention on this area. Although VTOC isn't a hardware/software co-development tool per se, it does provide a mechanism for you to obtain C/C++ equivalents of your Verilog models, which can then be integrated into your co-development environment.

But why isn't everyone doing it? Having become aware of the concept of translating Verilog to C/C++, you start to wonder why everyone isn't doing it. In fact, there are a few other companies and groups with their toes in the water, but no one who appears to be going head-to-head against Tenison.

For example, Cynergy used to have a product called Afterburner which appears to have offered somewhat similar capabilities to Tenison's VTOC, but Cynergy is now out of business (rumor has it that they tried to develop too many products simultaneously and simply ran out of money).

Forte has a product called Cynchronizer that is similar to VTOC. However, Cynchronizer only produces C++ code that functions with Forte's Cyn++ libraries. This is a severe limitation for first-time users who don't already have access to Forte products, because they would have to buy into the whole Forte design flow just to use the Cynchronizer tool.

There is also a public domain tool called Verilator that translates Verilog into C and SystemC. However, a friend of mine -- Tom Dillon, President of Dillon Engineering-- ran a few test circuits through VTOC and Verilator. Tom reported that Verilator was way less "forgiving" than VTOC and that he was not able to run any sizable test cases through it (apart from a canned example provided with the product). Furthermore, Tom observed that simply looking at the output shows that the way in which Verilator performs its translation means that the speedup simply isn't there.

Of course, it would be possible for one of the "big boys" like Cadence, Synopsys, or Mentor to throw a team together to generate a translator internally, but, to the best of my knowledge, none of them have any plans in this area. Also, truth to tell, I think that generating optimized cycle-accurate C/C++ models that provide the simulation speedup offered by VTOC is a non-trivial problem. The folks at Tenison know an awful lot about this sort of thing and have been honing their tool for several years, which I believe gives them a significant head start.

Will VTOC be of any use in your projects? Only you can tell. Once nice thing is that you can download a copy of the product and the manual from Tenison's web site and request a free evaluation license. Another advantage is that, being small, Tenison are very interested in receiving user feedback and acting on it in a fast and furious manner. So why not take the time to have a play, and let me know how you get on. Enjoy!